Freescale Semiconductor /MKL28T7_CORE1 /SCG /SIRCCSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SIRCCSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)SIRCEN 0 (0)SIRCSTEN 0 (0)SIRCLPEN 0 (0)LK 0 (0)SIRCVLD 0 (0)SIRCSEL

SIRCSTEN=0, SIRCLPEN=0, SIRCEN=0, SIRCSEL=0, SIRCVLD=0, LK=0

Description

Slow IRC Control Status Register

Fields

SIRCEN

Slow IRC Enable

0 (0): Slow IRC is disabled

1 (1): Slow IRC is enabled

SIRCSTEN

Slow IRC Stop Enable

0 (0): Slow IRC is disabled in Stop modes

1 (1): Slow IRC is enabled in Stop modes

SIRCLPEN

Slow IRC Low Power Enable

0 (0): Slow IRC is disabled in VLP modes

1 (1): Slow IRC is enabled in VLP modes

LK

Lock Register

0 (0): Control Status Register can be written.

1 (1): Control Status Register cannot be written.

SIRCVLD

Slow IRC Valid

0 (0): Slow IRC is not enabled or clock is not valid

1 (1): Slow IRC is enabled and output clock is valid

SIRCSEL

Slow IRC Selected

0 (0): Slow IRC is not the system clock source

1 (1): Slow IRC is the system clock source

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